The bottleneck is not making the silicon run

It's establishing that what it computes is what was specified. That question arrives in a different form for an accelerator vendor, an operator running its own parts, and a program approaching tapeout, but it's the same question, and it's where the schedule goes.

Why the schedule goes where it does

A new part reaches first output quickly. The work that follows is establishing that the output is correct, and that work is done by testing: differential comparison against a reference, coverage over representative inputs, and engineering judgment about when enough is enough.

Testing closes slowly, it reopens on the next release, and it never reaches certainty. Every vertical below is a different team meeting that same property from a different direction, with a different amount already committed by the time they meet it.

Two engagements, divided by what is already committed

Every vertical above is served by one of two engagements, and which one depends on where the silicon is in its life rather than on the industry it ships into. Model bring-up is for a part that has already been bought and is waiting to earn. Design signoff is for a part that is still a netlist, where what can be claimed at tapeout is still being decided.

Both run the same four products against a device the customer names. The technical argument does not change between them. The cost of being wrong does.

Want the tools before the engagement? The four products

Does one of these describe the program in front of you?